As one of many scaling techniques for increasing the density of semiconductor devices, a multi gate transistor has been proposed, in which a fin- or nanowire-shaped multi-channel active pattern (or silicon body) is formed on a substrate. A gate is formed on a surface of the multi-channel active pattern.
Since the multi gate transistor uses a three-dimensional channel, scaling of the multi gate transistor can be performed with ease. Furthermore, current controlling capability can be improved without increasing the gate length of the multi gate transistor. A short channel effect (SCE) in which an electric potential of a channel region is affected by a drain voltage, may be effectively suppressed.